Research output

Publications

Peer-reviewed contributions by TCAL members across computer architecture and design, reliability, energy efficiency, hardware security, and digital systems.

TCAL publishes at leading international computer architecture and design venues, including MICRO ISCA HPCA DAC DATE

2012

[MAM]  Area-time efficient multi-modulus adders and their applications   
Haridimos T. Vergos and Dimitris Bakalis
In Microprocessors and Microsystems, Volume: 36, Issue: 5, pp. 409-419, July 2012

[TC]  On Modulo 2^n+1 Adder Design   
Haridimos T. Vergos and Giorgos Dimitrakopoulos
In IEEE Transactions on Computers, Volume: 61, Issue: 2, pp. 173-186, February 2012

[DSD]  SUT-RNS Residue-to-Binary Converters Design   
Evangelos Vassalos, Dimitris Bakalis, and Haridimos T. Vergos
15th Euromicro Conference on Digital System Design (DSD 2012), Cesme, Izmir, Turkey, September 2012, pp. 65-72


2011

[INTEGRATION]  Efficient modulo 2n±1 squarers   
Dimitris Bakalis, Haridimos T. Vergos, and Anastasia Spyrou
In Integration, the VLSI Journal, Volume: 44, Issue: 3, pp. 163-174, June 2011

[FPT]  FPGA power consumption measurements and estimations under different implementation parameters   
Dimitrios Meidanis, Konstantinos Georgopoulos, and Ioannis Papaefstathiou
IEEE International Conference on Field-Programmable Technology (FPT 2011), New Delhi, India, December 2011, pp. 1-6

[DSD]  Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion   
Evangelos Vassalos, Dimitris Bakalis, and Haridimos T. Vergos
14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2011), Oulu, Finland, August-September 2011, pp. 468-475

[CSSP]  On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors   
Evangelos Vassalos, Dimitris Bakalis, and Haridimos T. Vergos
In Circuits, Systems, and Signal Processing, Volume: 30, Issue: 6, pp. 1445-1461, December 2011

[DSP]  On the use of double-LSB and signed-LSB encodings for RNS   
Evangelos Vassalos, Dimitris Bakalis, and Haridimos T. Vergos
17th International Conference on Digital Signal Processing (DSP 2011), Corfu, Greece, July 2011, pp. 1-6

[ICECS]  Test data compression based on the reuse of parts of the dictionary entries   
Panagiotis Sismanoglou and Dimitris Nikolos
18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon, December 2011, pp. 538-541


2010

[ISVLSI]  A Family of Area-Time Efficient Modulo 2n+1 Adders   
Haridimos T. Vergos
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), Lixouri, Kefalonia, Greece, July 2010, pp. 442-443

[DSD]  Area-Efficient Multi-moduli Squarers for RNS   
Dimitris Bakalis and Haridimos T. Vergos
13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2010), Lille, France, September 2010, pp. 408-411

[INTEGRATION]  Fast modulo 2n+1 multi-operand adders and residue generators   
Haridimos T. Vergos, Dimitris Bakalis, and Costas Efstathiou
In Integration, the VLSI Journal, Volume: 43, Issue: 1, pp. 42-48, January 2010

[CN]  High-speed, in-band performance measurement instrumentation for next generation IP networks   
Dimitrios P. Pezaros, Konstantinos Georgopoulos, and David Hutchison
In Computer Networks, Volume: 54, Issue: 18, pp. 3246-3263, December 2010

[JCSC]  On Implementing Efficient Modulo 2n + 1 Arithmetic Components   
Haridimos T. Vergos and Dimitris Bakalis
In Journal of Circuits, Systems and Computers, Volume: 19, Issue: 5, pp. 911-930, August 2010

[ISVLSI]  SUT-RNS Forward and Reverse Converters   
Evangelos Vassalos, Dimitris Bakalis, and Haridimos T. Vergos
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), Lixouri, Kefalonia, Greece, July 2010, pp. 11-16