Research output

Publications

Peer-reviewed contributions by TCAL members across computer architecture and design, reliability, energy efficiency, hardware security, and digital systems.

TCAL publishes at leading international computer architecture and design venues, including MICRO ISCA HPCA DAC DATE

2018

[SEMANTiCS]  Ontological Development of a Medical Decision Making System (MDMS)   
Vaios Papaioannou and George-Peter K. Economou
Posters and Demos Track of the 14th International Conference on Semantic Systems (SEMANTiCS 2018), Vienna, Austria, September 2018

[IOLTS]  Periodic Aging Monitoring in SRAM Sense Amplifiers   
Helen-Maria Dounavi, Yiorgos Sfikas, and Yiorgos Tsiatouhas
24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), Platja d'Aro, Spain, July 2018, pp. 12-16

[MOCAST]  Aging monitoring in SRAM sense amplifiers   
Helen-Maria Dounavi, Yiorgos Sfikas, and Yiorgos Tsiatouhas
7th International Conference on Modern Circuits and Systems Technologies (MOCAST 2018), Thessaloniki, Greece, May 2018, pp. 1-4

[DATE]  A novel fault tolerant cache architecture based on orthogonal latin squares theory   
Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, and Dimitris Nikolos
Design, Automation & Test in Europe Conference & Exhibition (DATE 2018), Dresden, Germany, March 2018, pp. 1429-1434

[ARC]  Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design   
Konstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos, Apostolos Dollas, Dionysios N. Pnevmatikatos, and Ioannis Papaefstathiou
14th International Symposium on Applied Reconfigurable Computing (ARC 2018), Santorini, Greece, May 2018, pp. 459-470

[ARC]  HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE   
Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, and Iakovos Mavroidis
14th International Symposium on Applied Reconfigurable Computing (ARC 2018), Santorini, Greece, May 2018, pp. 724-736


2017

[MICRO]  Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs       
G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, P. Lawthers, and S. Das
Proceedings of the 50th IEEE/ACM International Symposium on Microarchitecture, Boston, MA, USA, October 2017
  [HiPEAC Paper Award]

[IOLTS]  Voltage Margins Identification on Commercial x86-64 Multicore Microprocessors       
G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, C. Magdalinos, D. Gizopoulos
Proceedings of the 23rd IEEE Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, July 2017

[TDMR]  An Agile Post-Silicon Validation Methodology for the Address Translation Mechanisms of Modern Microprocessors   
G. Papadimitriou, D. Gizopoulos, A. Chatzidimitriou, and R. Morad
In IEEE Transactions on Device and Materials Reliability, Volume: 17, Issue: 1, pp. 3-11, March 2017

[SELSE]  A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs    
G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, G. Favor, K. Sankaran, and S. Das
In IEEE Silicon Errors in Logic – System Effects, Boston, MA, USA, March 2017

[EnESCE]  An Energy-Efficient and Error-Resilient Server Ecosystem Exceeding Conservative Scaling Limits    
K. Tovletoglou, C. Chalios, G. Karakonstantis, L. Mukhanov, H. Vandierendonck, D. S. Nikolopoulos, P. Koutsovasilis, M. Maroudas, C. Antonopoulos, C. Kalogirou, N. Bellas, S. Lalis, M. Rafique, S. Venugopal, A. Prat-Perez, A. Diavastos, Z. Hadjilambrou, P. Nikolaou, Y. Sazeides, P. Trancoso, G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, and D. Gizopoulos
Workshop on Energy-Efficient Servers for Cloud and Edge Computing, Stockholm, Sweden, January 2017

[DATE]  A novel way to efficiently simulate complex full systems incorporating hardware accelerators   
Nikolaos Tampouratzis, Konstantinos Georgopoulos, and Yannis Papaefstathiou
Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, Switzerland, March 2017, pp. 658-661


2016

[ICCD]  Unveiling Difficult Bugs in Address Translation Caching Arrays for Effective Post-Silicon Validation       
G. Papadimitriou, D. Gizopoulos, A. Chatzidimitriou, T. Kolan, A. Koyfman, R. Morad, and V. Sokhin
Proceedings of the 34th IEEE International Conference on Computer Design, Phoenix, AZ, USA, October 2016

[IOLTS]  ISA-Independent Post-Silicon Validation for the Address Translation Mechanisms of Modern Microprocessors       
G. Papadimitriou, A. Chatzidimitriou, D. Gizopoulos, and R. Morad
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, Sant Feliu de Guixols, Spain, July 2016

[VTS]  Microprocessor Reliability-Performance Tradeoffs Assessment at the Microarchitecture Level   
S. Tselonis, M. Kaliorakis, N. Foutris, G. Papadimitriou, and D. Gizopoulos
Proceedings of the 34th IEEE VLSI Test Symposium, Las Vegas, NV, USA, April 2016

[IOLTS]  Conditional soft-edge flip-flop for SET mitigation   
Panagiotis Sismanoglou and Dimitris Nikolos
22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), Sant Feliu de Guixols, Spain, July 2016, pp. 227-232

[ICECS]  Extending the viability of power signature - Based IP watermarking in the SoC era   
George Blanas and Haridimos T. Vergos
IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), Monte Carlo, Monaco, December 2016, pp. 281-284

[ISQED]  Low capture power dictionary-based test data compression   
Panagiotis Sismanoglou and Dimitris Nikolos
17th International Symposium on Quality Electronic Design (ISQED 2016), Santa Clara, CA, USA, March 2016, pp. 289-294